Openings at Magma Design Automation, Noida Bangalore

Position 1:
Experience: 4 to 10 Yrs
Location: Bangalore
1. Strong skills in EDA/ASIC Digital backend flow.
2. Familiar with a range of industry standard EDA tools and methods for the design, implementation, and verification Digital ICs.
3. Knowledge of the complete digital design process from schematic to layout including understanding devices, simulation, timing and place & route analysis is desired.
4. Experience with static timing analysis is a must and development using scripting language such as Tcl is highly desired.
5. Candidate should have Btech/Mtech from Electronics/CS background.
5. Should be a good team player and effective communication skills
=======================================

Position 2:
Experience: 3 to 7 Yrs
Location: Noida / Bangalore
1. Strong skills in EDA/ASIC Digital flow.
2. Candidate must have good knowledge of RTL synthesis and must have used industry standard synthesis and formal verification tool.
3. Must have good knowledge of at least one scripting language (Perl/Tcl).
4. Should be a good team player and effective communication skills.
5. Candidate should have Btech/Mtech from EE/CS background

Send your resumes to: msrini@magma-da.com with SUBJECT in the following format
Resume: Abhishek Bachan, BTech in EC from IIT Madras, 3 years experience in VLSI

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EMBEDDED VLSI JOBS @ KYOCERA BANGALORE

About Company : If you are in wireless, discover the global champion that is serving some real hot aces - Kyocera Wireless. The place where cutting edge technology and best-in-class talent enable end-to-end product development. Our core technology supports Kyocera’s global marketing strategies. The challenge is now to develop products for 2010 and beyond!

Being part of the Japan-headquartered $10.5 billion Kyocera group, we have the vision, resources and market strength to give our technology professionals the challenge of being ahead of the market.

Kyocera Wireless’ core technology areas at its R&D facility in Bangalore, include Next Generation Mobile Networks, iBurst and PHS. We invite the very best in the industry to move out of their present comfort zones and seek the excitement of Kyocera. In return, expect freedom and a conducive environment that encourage you to take ownership of your initiatives.

Job Title : Engineer-L2 Requirement

Experience : 3 - 7 Years

Job Description : Will be responsible to design and develop and testing of MAC related software for Next Generation PHS systems.

Desired : Should be proficient in C++, at least 2 years of coding experience in C++.
Should have worked on any wireless Layer-2 (MAC) protocol (eg: WiMAX, 802.11, GPRS, GSM, CDMA, WCDMA, etc) for at least 1 year.
Should have at least one year of working experience in any of RTOS, VxWorks or Embedded Linux is proffered.
Should be proficient in OS internals and IPC.
Should be proficient in OO concepts.
Working knowledge of any CASE tool (Rhapsody, Telelogic-Tau, Ratinoal-Rose, etc.) is preferred.
Around 4-6 years of relevant work experience is essential.

Location : Bangalore

Contact Kyocera Wireless (India) Pvt Ltd

Apply : Email ur cv to wireless.career(at)kyocera-wireless.com

Website : www.kyocera-wireless.com

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EMBEDDED VLSI JOBS @ FREESCALE SOFTWARE BANGALORE

About Company : FreeScale Software India Pvt Ltd does cutting edge work on the embedded platform by developing and porting multiple solutions to FreeScale reference platforms

Job Title : BLR- -Symbian BSP Engineers

Experience : 2 - 6 Years

Education : B.Tech/B.E. , M.Tech

Job Description : Designing, Development and Testing of Embedded Software (Mainly Device Driver) for Cellular and Application Processors in Symbian OS.

The main activities involved will be following:
Understanding the Hardware Architecture/HW blocks on mobile Apps Processor ICs
Implementation of Symbian driver modules in C/C++ and/or assembly for embedded mobile chipsets/platforms
Participation in Software Quality Process (code/design reviews, etc.)
Integration of the modules into the system and conduction of tests at the integration level, automation of tests, documentation of the test results

Desired : Strong programming skills in C/C++ (assembly will be an advantage)
Strong understanding of OS and real-time OS concepts
Knowledge on ARM processor architecture. Working knowledge in ARM a plus.
Strong understanding of hardware/computer architecture and interfaces
Must have worked in Device driver development. Working knowledge in Symbian Device Drivers a plus.
Working knowledge in Keypad, USB, UART, Flash memory, MMC/SD, Timers, I2C, SSI drivers a plus.
Hardware level development/debugging on embedded platforms using debuggers
Knowledge of the Source code version control tools like Clearcase, CVS, etc.
Should have good communication skills to communicate at all levels within the organization

Location : Bangalore

Apply : Email ur cv to FSLHR1(at)freescale.com

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VLSI - Training Delivery Head Jobs Bangalore

Job Title: Training Delivery Head - VLSI
Company Name: CG-Coreel
Experience in years: More than 5 years (Blend of Industry & Academic experience.)
Skills: Verilog, VHDL, FPGA, ASIC
Salary Range: Best in the industry
Job Location: Bangalore
Apply Email: rajesh.shetty@coreel.com
Contact number: 9741322771

Regards
Rajesh Shetty
Sales Manager - Training Business
Sandeepani - School of VLSI Design
(A division of CG-CoreEl Programmable Solutions Pvt. Ltd.)
# 863-D, 12th Main, III Block, Koramangala, Bangalore - 560034, INDIA
Ph: 91-80-25529733/34, Mob: 9741322771 visit us at www.sandeepani-vlsi.com

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VLSI opening for 1+ year experienced

Hi there are the following openings in a major VLSI firm in hyderabad.
Please send in the resumes to shrihari.a@gmail.com if you have a matching profile with CV FOR OPENING in the subject line .
"FRESHERS DONT SEND IN THE RESUMES"

Education: Engineering Degree

Exp: Minimum 1+ year


Position: Engineer

No of Positions: 10



1. Physical Design

Key Responsibilities

This is a full time position in our Hyderabad office. As a Physical Design Engineer you will be responsible for the entire Physical implementation of our chips designed for PC, Handheld, Entertainment or DTV requirements. This position requires interface with large front-end design teams in US, Canada and India. This may require travel to our other Design Centers.

The Physical Design Engineer will be responsible for execution of block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks.

In addition, it is desirable to have:
 Effective written and oral communication skills in English
 Understanding Verilog HDL
 Understanding Deep Submicron effects such as 90nm and below
 Understanding OCV, DFM, DFY

Job Requirements:

 Minimum 1 year of ASIC physical design experience.
 Reasonable Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
 Hands on experience and reasonable knowledge in Cadence and Synopsys Physical Implementation Tools
 Scripting Language with PERL, TCL, AWK, shell scripting is desirable.
 Familiar with Physical Verification will be a plus.

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Great opportunities in vlsi industry

Make Your Career in VLSI

Do part time course @ TIIT Bangalore.
And get placed in VLSI Companies!

Attend Seminar on VLSI-ASIC Design Engineering
On 19th April 2008

Time : Evening @ 5.30pm to 6.30pm

Venue:
TIIT Pvt Ltd
# 18, 1st Floor, Palavalli Plaza
100 Feet Ring Road
2nd Stage BTM Layout,
Bangalore-560076.

Call for seat Reservation to
080-26789654,41460758
Or
Mail to: blrtraining@tiit.in
More Info: www.tiit.in

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VLSI Design engineers

Openings for Design engineers, Layout, digital design, verification, testing and physical Design Engineers
Hi,
Freescale is presently looking for engineers with experience 1 – 3 yrs for th following skill sets:

Analog Design Team:

- Analog Layout & Design

- Standard Cell Design & Layout

Physical Design Team:

- Cadence/TI Flow

- Must have worked on Complete Tape out

Verification Team:

- RTL Design/ STA

- Verilog/DFT/MBIST

Testing team:

If you want to apply for other top VLSI companies like Intel,TI,AMD etc. then just send your resumes, i will forward it to through my friends who are working there and give reference to you. my mail id is deepika.reddy85@gmail.com

"Freshers please dont apply"

Work Location : Bangalore, Noida, Hyderabad

Pl fill in the following details and send them along with the resume

Current CTC:
Expected CTC:
Notice period:

Regards,
Deepika

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URGENT OPENINGS IN VLSI

*Technical lead (positions - 2)*
Role: Will be initially based in US with responsibility of one of the US
customers. Role will include Communication with Customer in US as well
as their counterpart based in India. Excellent Communication Skills,
Zeal to drive things to closure and possession of basic Leaderships
qualities are fundamental requirements. Good technical knowledge in
Analog/Mixed Signal circuit design area is desired.
*Minimum experience 3 years . *

* Wireless RF Physical Design Lead (positions - 1)*
Role: Will be leading the Sankalp activity with one of the top 15 Global
Semiconductor Companies. Will be initially based in Bangalore. Good
Communication skills with leadership qualities and sustained urge to get
things done are the basic requirements. Good technical knowledge in
Analog/Mixed Signal circuit design area is desired.
* Minimum experience 3 years . *

* Senior Design Engineer (Position - 4)*
Role: Will be leading small team involved in developing and delivering
analog modules (Spec to GDS2) with perfection. Conscience driven
Leadership qualities with excellent interpersonal skills are desirable.
Passion and drive for technical depth in Analog / Mixed signal is a
must. Positioning will be in Hubli, Karnataka.
* Minimum experience 2 year .*

Interested people can send their resume to sali.mspl@gmail.com

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Big Opening in Freescale Semiconductor

Hi Every body ,

Here there is big opening in our company.
Following are the details:

1. DSP engineer : 3+ yrs experience
2.memory circuit design engineers: 3+ yrs experience
3.Embeded/device driver/RTOS engineer : 3+ yrs
experience

--Amit
9999652619

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VLSI (Chip Designing)TRAINING FIRST TIME IN MUMBAI

World Class Semiconductor Technologies.

We undertake training as well as projects for B.E, B.Tech, M.S., M.Tech, PhD level student in Front end & Back hand in VLSI.

Limited Offer: Discounted price of Rs. 54,000 & service tax waived off for limited seats. (Original Price : Rs. 66,500 + Service tax)

Course Duration: 4 months. (3 hours Training / 3 hours Lab).

Batch Start Date: 1st Feb 2008.
Last Date of admission: 30th JAN 2008.

Oppurtunitites : Samsung, LG, Motorola, Nokia, Hughes, siemens, Infosys, Sony, Wipro, Xius, Patni, Sasken, Mphasis, Satyam, Freescale, Taxas Instruments, Tata Elxsi, Delphi, Synopsys, Cadence, Synplicity, Mentor Graphics, Altera, Global Edge, ST microelectronic, Axes tech, Netlogic, nVIDIA, Honeywell, Infineon, Magma, Syschip, AMD, ARM, Syschip, National semiconductor ,chip vision, verizon, tsmc, tensilica, sun microsystem, Flextronic, Genesys microchip, Larsen & Tourbo, Xilinx, KPIT, IBM, HP, INTEL,DELL.

ALEX – (MUMBAI).
Symbian.in@gmail.com

9987114916 / 9930037389

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Job in VLSI, VHDL

Experience 1-3 yrs

Company: Scientific Mes Technik Pvt Ltd, B-14, Polograund, Industrial Estate, Indore-15 (MP)
Ph: 0731 2422330-33
Email: info@scientificindia.com
cont: Mr Prabhu Sir
Ref: A K Jain (Testing Engr)
Note: Person who works on ALTERA get prefered.

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silicatec requires vlsi trainers

Silicatec, USA based VLSI Institute needs Professor and Trainer

The VLSI division at the Silicatec invites applications for Professor & Trainer position. We seek outstanding applicants with teaching and research interests in System-On-Chip/FPGA/ASIC design for Consumer and Mobile technology areas. Silicatec seeks an individual to join our core faculty in this area and to lead the development of new research and teaching for VLSI programs. We are especially interested in candidates who can contribute to the diversity and excellence of the academic community through their research, teaching, and service.

Rank: VLSI Trainer

Location: Bhubaneswar

Experience: Should have minimum 2+ years of teaching experience

Qualification: BE/BTECH/M.S. or Ph.D. in Computer Engineering, Electrical Engineering, or related field with emphasis on chip design with complete understanding of SOC/ASIC/FPGA design flow; demonstrated excellence in computer and networking architecture; a strong record of teaching RTL coding, Synthesis, Timing analysis, Circuit Design, DFT, Physical design and verification; proven distinction in university teaching at the graduate and undergraduate levels for VLSI using latest EDA (Cadence, Mentor, Synopsys & Magma tools.

If you are interested in this opening, please send us your updated profile mentioning your current ctc, expected ctc and notice period information.

regards,
Manjeet@silicatec.com

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